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Divyansh Agrawal describes Qwenputer, an experiment that adds a 32-bit RISC-V CPU to Qwen3.5 4B’s weights and uses Gated DeltaNet state as RAM. He reports that it passes official RISC-V tests and completed an 18-million-instruction free-running test without errors; these results come from his report, not an independent evaluation included in the source material.
Researcher Divyansh Agrawal has described Qwenputer, an experimental version of Qwen3.5 4B with a 32-bit RISC-V CPU compiled into its weights. The design uses the model’s Gated DeltaNet state as addressable RAM, allowing the CPU to execute during model forward passes rather than through an external tool or runtime. Agrawal reports that the processor passes official RISC-V tests and ran 18 million instructions without an error, making the project a demonstration of computation embedded within a language model.
According to Agrawal’s report, the CPU implements the RV32IM instruction set, with the Zba extension and a small bignum unit for larger arithmetic. It occupies 11 layers placed ahead of Qwen3.5’s 32 layers. The CPU is described as deterministic: its registers, program counter and memory are represented in state rows, and execution proceeds through a token trace generated by the model.
The memory scheme relies on changes to Gated DeltaNet (GDN), a recurrent attention mechanism used in Qwen3.5. Agrawal says that setting the gate to 1 prevents stored state from fading, while a write strength of 1 replaces a selected value. One-hot keys can select individual rows for writing and reading. He says this makes the state function as exact, addressable memory for the processor.
Agrawal reports that the CPU passes the official riscv-tests, that its program results match QEMU, and that it completed an 18-million-instruction free-running run without correction from a reference machine. The model can also execute C and MicroPython code, though the report describes that execution as slow. The project is available through Hugging Face and ModelScope, with code on GitHub, according to the report.
A CPU Inside Model Inference
Qwenputer offers a concrete demonstration of a language model carrying out structured computation inside its own forward passes. Instead of asking an external tool to run a program, the model’s added layers maintain CPU state and perform instructions as it generates tokens. That distinction matters for researchers exploring whether neural architectures can support reliable, repeatable computation alongside text generation.
The reported use of GDN state as RAM is also relevant to model design. Unlike an attention key-value cache that grows with the conversation, Agrawal says a GDN head’s state remains a fixed size. The experiment suggests one way to use recurrent state for memory with explicit addresses. It does not, by itself, show that this approach is faster or more useful than conventional processors or external tools; the source describes execution as relatively slow and provides no independent performance comparison.
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From Recurrent Memory to CPU
Qwenputer builds on Qwen3.5, which uses a hybrid architecture. Agrawal says three out of every four attention layers use Gated DeltaNet, a linear recurrent mechanism that maintains state matrices. Prior work, including a 2021 paper by Imanol Schlag, Kazuki Irie and Jürgen Schmidhuber, described delta-rule linear attention as an associative memory or “fast weights.” Agrawal presents Qwenputer’s contribution as making that memory exact and addressable enough to support a CPU.
The CPU is added by setting weights directly with a compiler, rather than training the model to learn the processor. During execution, instruction steps are represented by generated tokens that identify an address, carry a value and end with a step marker. Agrawal says the model’s original weights remain unchanged, while the computer weights are added on top. A driver called RvChat loads firmware into GDN state and keeps the execution trace out of Qwen’s ordinary layers.
““The RNN inside Qwen3.5 can be exact RAM.””
— Divyansh Agrawal, Qwenputer’s creator
Independent Testing and Limits
The performance and reliability figures in the available material are Agrawal’s reported results; no independent replication, test logs or third-party assessment are supplied. The report says the CPU passes official tests and matches QEMU, but it does not provide detailed benchmark data, execution speed, memory capacity or power and hardware costs. It is also unclear how the design performs across different prompts, model-serving setups or longer practical workloads.
The description establishes that the CPU runs in the model’s forward passes, but does not fully quantify how much added compute is required for each instruction or how the experiment compares with ordinary tool-based code execution. The source also mentions experimental in-model file storage and related follow-up work, but the supplied material does not provide enough detail to assess those capabilities.
Code and Replication Ahead
Agrawal says Qwenputer’s model files are available through Hugging Face and ModelScope, and that its code is on GitHub. Those releases give other researchers a route to inspect the implementation and attempt to reproduce the reported RISC-V tests and long free-running run. No formal independent evaluation or follow-up milestone is specified in the supplied report.
The next useful evidence would include reproducible instructions, test outputs and performance measurements that show how the model behaves under varied workloads. Until such results are available, Qwenputer is best understood as a reported experimental demonstration of an embedded CPU, rather than evidence that language models can replace conventional processors or external execution tools.
Key Questions
What is Qwenputer?
Qwenputer is an experimental version of Qwen3.5 4B with a RISC-V CPU compiled into its weights, as described by its creator, Divyansh Agrawal.
Does it use an external tool to run programs?
Agrawal says the CPU runs within the model’s forward passes, without an external runtime or tool call. A driver loads firmware into the model state, but the CPU execution itself is described as internal.
What kind of processor does it implement?
The reported design is a 32-bit RV32IM RISC-V core, with the Zba extension and a small bignum unit. Agrawal says it can run C and MicroPython, though relatively slowly.
How well has the CPU been tested?
Agrawal reports that it passes official riscv-tests, matches QEMU results and completed 18 million free-running instructions without an error. The supplied source does not include an independent replication of those results.
Can Qwenputer replace a regular computer?
The report does not claim that. Agrawal says it is not a Linux-class chip, and the described implementation is a research experiment rather than a demonstrated replacement for conventional processors.
Source: divagr.com
